The present invention relates to a digital data processor and, more particularly, to such a processor having a unit for unscrambling a string of data which have been received in a scrambled.
In order to reduce an error rate of information to be transferred or reproduced, a data-scrambling technique is widely employed. For example, in a compact disk (CD) system, an analog signal representative of music information or the like is converted into a string of digital data, each data being called a "symbol" and consisting of eight bits. Each symbol data is modulated to fourteen bits through well-known Eight-to-Fourteen Modulation (EFM). The string of modulated symbol data is scrambled and then recorded on a compact disk together with parity information that is used for making an error correction.
In a playback or reproduce processing therefore, the data recorded into the disk are read out therefrom and then subjected to an EFM demodulation. The string of demodulated symbol data is supplied to an error correction processing unit which executes a so-called C1 correction and C2 correction. Then the corrected data is transferred to an unscrambling unit in order to obtain the unscrambled data string. The unscrambling unit includes a semiconductor memory. The string of data from the error correction processing unit is once written into the memory. The data stored in the memory are thereafter read out in the order to be unscrambled.
However, the semiconductor memory employed by the prior art in the unscrambling unit has only one set of address terminals. A write address and a read address are supplied in common to the set of address terminals. Moreover, in a case where the write and read addresses have the same value, the same word line is driven to select memory cells arranged in the same row in both a data write operation and a data read operation. For this reason, when the string of symbol data derived from the error correction processing unit is written into the memory in the order of the address thereof, a read address calculation circuit is required to read the data from the memory in the order to be unscrambled. Or else, a write address calculation circuit is required to write the string of data into the memory at addresses corresponding to the order to be unscrambled. The data written into the memory is read out in the order of the address. Particularly, in a case where the EFM demodulation, C1 and C2 correction and read and write address calculation are performed by a single data processor, these processing operations must be performed in time-sharing, so that a very high speed processor is required.